# 1 "FWlib/apt32f102_i2c.c"
# 1 "E:\\APT_3RTD\\Tuya_AC_3RTD\\Source//"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "FWlib/apt32f102_i2c.c"
# 17 "FWlib/apt32f102_i2c.c"
# 1 "include/apt32f102_i2c.h" 1
# 24 "include/apt32f102_i2c.h"
# 1 "include/apt32f102.h" 1
# 23 "include/apt32f102.h"
# 1 "include/apt32f102_types_local.h" 1
# 63 "include/apt32f102_types_local.h"
typedef signed char S8_T;
typedef short S16_T;
typedef long S32_T;


typedef unsigned char U8_T;
typedef unsigned short U16_T;
typedef unsigned long U32_T;
typedef unsigned long long U64_T;


typedef float F32_T;
typedef double F64_T;


typedef U8_T B_T;
# 100 "include/apt32f102_types_local.h"
typedef enum {ENABLE = 1, DISABLE = !ENABLE} ClockStatus, FunctionalStatus;
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;




typedef volatile U32_T CSP_REGISTER_T;
typedef volatile U16_T CSP_REGISTER16_T;
typedef volatile U8_T CSP_REGISTER8_T;




typedef unsigned char UINT8;
typedef signed char SINT8;


typedef unsigned short UINT16;
typedef signed short SINT16;


typedef unsigned long UINT32;
typedef signed long SINT32;

typedef void VOID;
typedef signed char CHAR;
typedef unsigned char BOOL;
typedef signed long TIME_T;

typedef float SINGLE;



typedef double DOUBLE;

typedef struct
{
  unsigned bit0 : 1;
  unsigned bit1 : 1;
  unsigned bit2 : 1;
  unsigned bit3 : 1;
  unsigned bit4 : 1;
  unsigned bit5 : 1;
  unsigned bit6 : 1;
  unsigned bit7 : 1;
} REG8;

typedef struct
{
  unsigned bit0 : 1;
  unsigned bit1 : 1;
  unsigned bit2 : 1;
  unsigned bit3 : 1;
  unsigned bit4 : 1;
  unsigned bit5 : 1;
  unsigned bit6 : 1;
  unsigned bit7 : 1;
  unsigned bit8 : 1;
  unsigned bit9 : 1;
  unsigned bit10: 1;
  unsigned bit11: 1;
  unsigned bit12: 1;
  unsigned bit13: 1;
  unsigned bit14: 1;
  unsigned bit15: 1;
} REG16;






typedef char STRING_3[4];
typedef char STRING_5[6];
typedef char STRING_8[9];
typedef char STRING_10[11];
typedef char STRING_12[13];
typedef char STRING_16[17];
typedef char STRING_24[25];
typedef char STRING_30[31];
typedef char STRING_32[33];
typedef char STRING_48[49];
typedef char STRING_50[51];
typedef char STRING_60[61];
typedef char STRING_80[81];
typedef char STRING_132[133];
typedef char STRING_256[257];
typedef char STRING_512[513];
# 24 "include/apt32f102.h" 2
# 1 "include/apt32f102_ck801.h" 1
# 85 "include/apt32f102_ck801.h"
typedef enum IRQn
{

        ISR_Restart = -32,
        ISR_Misaligned_Access = -31,
        ISR_Access_Error = -30,
        ISR_Divided_By_Zero = -29,
        ISR_Illegal = -28,
        ISR_Privlege_Violation = -27,
        ISR_Trace_Exection = -26,
        ISR_Breakpoint_Exception = -25,
        ISR_Unrecoverable_Error = -24,
        ISR_Idly4_Error = -23,
        ISR_Auto_INT = -22,
        ISR_Auto_FINT = -21,
        ISR_Reserved_HAI = -20,
        ISR_Reserved_FP = -19,
        ISR_TLB_Ins_Empty = -18,
        ISR_TLB_Data_Empty = -17,

        INTC_CORETIM_IRQn = 0,
        INTC_TIME1_IRQn = 1,
        INTC_UART0_IRQn = 2,
        INTC_GPIOA2_IRQn = 8,
} IRQn_Type;


void INTC_Init(void);
void force_interrupt(IRQn_Type IRQn);

void CK_CPU_EnAllNormalIrq(void);
void CK_CPU_DisAllNormalIrq(void);
# 25 "include/apt32f102.h" 2




typedef struct {
 volatile unsigned int ReservedA[4];
 volatile unsigned int CORET_CSR;
 volatile unsigned int CORET_RVR;
 volatile unsigned int CORET_CVR;
 volatile unsigned int CORET_CALIB;
 volatile unsigned int ReservedB[56];
 volatile unsigned int ISER;
 volatile unsigned int ReservedC[15];
 volatile unsigned int IWER;
 volatile unsigned int ReservedD[15];
 volatile unsigned int ICER;
 volatile unsigned int ReservedE[15];
 volatile unsigned int IWDR;
 volatile unsigned int ReservedF[15];
 volatile unsigned int ISPR;
 volatile unsigned int ReservedG[31];
 volatile unsigned int ICPR;
 volatile unsigned int ReservedH[31];
 volatile unsigned int IABR;
 volatile unsigned int ReservedI[63];
 volatile unsigned int IPR[8];
 volatile unsigned int ReservedJ[504];
 volatile unsigned int ISR;
 volatile unsigned int IPTR;
} CSP_CK801_T;



typedef volatile struct {
 volatile unsigned int IDR ;
 volatile unsigned int CEDR ;
 volatile unsigned int SRR ;
 volatile unsigned int CMR ;
 volatile unsigned int CR ;
 volatile unsigned int MR ;
 volatile unsigned int FM_ADDR ;
 volatile unsigned int Reserved ;
 volatile unsigned int KR ;
 volatile unsigned int IMCR ;
 volatile unsigned int RISR ;
 volatile unsigned int MISR ;
 volatile unsigned int ICR ;
} CSP_IFC_T ;



typedef volatile struct {
 volatile unsigned int IDCCR;
 volatile unsigned int GCER;
 volatile unsigned int GCDR;
 volatile unsigned int GCSR;
 volatile unsigned int CKST;
 volatile unsigned int RAMCHK;
 volatile unsigned int EFLCHK;
 volatile unsigned int SCLKCR;
 volatile unsigned int PCLKCR;
 volatile unsigned int _RSVD0;
 volatile unsigned int PCER0;
 volatile unsigned int PCDR0;
 volatile unsigned int PCSR0;
 volatile unsigned int PCER1;
 volatile unsigned int PCDR1;
 volatile unsigned int PCSR1;
 volatile unsigned int OSTR;
 volatile unsigned int _RSVD1;
 volatile unsigned int _RSVD2;
 volatile unsigned int LVDCR;
 volatile unsigned int CLCR;
 volatile unsigned int PWRCR;
 volatile unsigned int PWRKEY;
 volatile unsigned int _RSVD3;
 volatile unsigned int _RSVD4;
 volatile unsigned int OPT1;
 volatile unsigned int OPT0;
 volatile unsigned int WKCR;
 volatile unsigned int _RSVD5;
 volatile unsigned int IMER;
 volatile unsigned int IMDR;
 volatile unsigned int IMCR;
 volatile unsigned int IAR;
 volatile unsigned int ICR;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int RSR;
 volatile unsigned int EXIRT;
 volatile unsigned int EXIFT;
 volatile unsigned int EXIER;
 volatile unsigned int EXIDR;
 volatile unsigned int EXIMR;
 volatile unsigned int EXIAR;
 volatile unsigned int EXICR;
 volatile unsigned int EXIRS;
 volatile unsigned int IWDCR;
 volatile unsigned int IWDCNT;
 volatile unsigned int IWDEDR;
 volatile unsigned int IOMAP0;
 volatile unsigned int IOMAP1;
 volatile unsigned int CINF0;
 volatile unsigned int CINF1;
 volatile unsigned int FINF0;
 volatile unsigned int FINF1;
 volatile unsigned int FINF2;
 volatile unsigned int _RSVD6;
 volatile unsigned int ERRINF;
 volatile unsigned int UID0 ;
 volatile unsigned int UID1 ;
 volatile unsigned int UID2 ;
 volatile unsigned int PWROPT;
 volatile unsigned int EVTRG;
 volatile unsigned int EVPS;
 volatile unsigned int EVSWF;
 volatile unsigned int UREG0;
 volatile unsigned int UREG1;
 volatile unsigned int UREG2;
 volatile unsigned int UREG3;
} CSP_SYSCON_T;



 typedef volatile struct
 {
    volatile unsigned int EN;
    volatile unsigned int SWTRG;
    volatile unsigned int CH0CON0;
    volatile unsigned int CH0CON1;
    volatile unsigned int CH1CON0;
    volatile unsigned int CH1CON1;
    volatile unsigned int CH2CON0;
    volatile unsigned int CH2CON1;
 volatile unsigned int _RSVD0;
 volatile unsigned int _RSVD1;
 volatile unsigned int _RSVD2;
 volatile unsigned int _RSVD3;
    volatile unsigned int CH3CON;
 volatile unsigned int CH4CON;
 volatile unsigned int CH5CON;
 volatile unsigned int CH6CON;
 volatile unsigned int CH7CON;
 } CSP_ETCB_T, *CSP_ETCB_PTR;



typedef volatile struct
{
   volatile unsigned int TCH_CCR;
   volatile unsigned int TCH_CON0;
   volatile unsigned int TCH_CON1;
   volatile unsigned int TCH_SCCR;
   volatile unsigned int TCH_SENPRD;
   volatile unsigned int TCH_VALBUF;
   volatile unsigned int TCH_SENCNT;
   volatile unsigned int TCH_TCHCNT;
   volatile unsigned int TCH_THR;
   volatile unsigned int Reserved0;
   volatile unsigned int TCH_RISR;
   volatile unsigned int TCH_IER;
   volatile unsigned int TCH_ICR;
   volatile unsigned int TCH_RWSR;
   volatile unsigned int TCH_OVW_THR;
   volatile unsigned int TCH_OVF;
   volatile unsigned int TCH_OVT;
   volatile unsigned int TCH_SYNCR;
   volatile unsigned int TCH_EVTRG;
   volatile unsigned int TCH_EVPS;
   volatile unsigned int TCH_EVSWF;
} CSP_TKEY_T, *CSP_TKEY_PTR;



typedef volatile struct
{
   volatile unsigned int TCH_CHVAL[18];
   volatile unsigned int TCH_SEQCON[18];
} CSP_TKEYBUF_T, *CSP_TKEYBUF_PTR;



 typedef volatile struct
 {
    volatile unsigned int ECR;
    volatile unsigned int DCR;
    volatile unsigned int PMSR;
    volatile unsigned int Reserved0;
    volatile unsigned int CR;
    volatile unsigned int MR;
    volatile unsigned int SHR;
    volatile unsigned int CSR;
    volatile unsigned int SR;
    volatile unsigned int IER;
    volatile unsigned int IDR;
    volatile unsigned int IMR;
    volatile unsigned int SEQ[16];
    volatile unsigned int PRI;
    volatile unsigned int TDL0;
    volatile unsigned int TDL1;
    volatile unsigned int SYNCR;
    volatile unsigned int Reserved1;
    volatile unsigned int Reserved2;
    volatile unsigned int EVTRG;
    volatile unsigned int EVPS;
    volatile unsigned int EVSWF;
    volatile unsigned int ReservedD[27];
    volatile unsigned int DR[16];
    volatile unsigned int CMP0;
    volatile unsigned int CMP1;
 volatile unsigned int DRMASK;
 } CSP_ADC12_T, *CSP_ADC12_PTR;



 typedef volatile struct
 {
    volatile unsigned int CONLR;
    volatile unsigned int CONHR;
    volatile unsigned int WODR;
    volatile unsigned int SODR;
    volatile unsigned int CODR;
    volatile unsigned int ODSR;
    volatile unsigned int PSDR;
    volatile unsigned int FLTEN;
    volatile unsigned int PUDR;
    volatile unsigned int DSCR;
    volatile unsigned int OMCR;
    volatile unsigned int IECR;
 volatile unsigned int IEER;
 volatile unsigned int IEDR;
 } CSP_GPIO_T, *CSP_GPIO_PTR;

 typedef volatile struct
 {
 volatile unsigned int IGRPL;
    volatile unsigned int IGRPH;
 volatile unsigned int IGREX;
    volatile unsigned int IO_CLKEN;
 } CSP_IGRP_T, *CSP_IGRP_PTR;



 typedef volatile struct
 {
    volatile unsigned int DATA;
    volatile unsigned int SR;
    volatile unsigned int CTRL;
    volatile unsigned int ISR;
    volatile unsigned int BRDIV;
    volatile unsigned int ReservedA[20];
 } CSP_UART_T, *CSP_UART_PTR;



typedef struct
{
 volatile unsigned int CR0;
 volatile unsigned int CR1;
 volatile unsigned int DR;
 volatile unsigned int SR;
 volatile unsigned int CPSR;
 volatile unsigned int IMSCR;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int ICR;
} CSP_SSP_T, *CSP_SSP_PTR;



typedef struct
{
 volatile unsigned int CR;
 volatile unsigned int TXCR0;
 volatile unsigned int TXCR1;
 volatile unsigned int TXBUF;
 volatile unsigned int RXCR0;
 volatile unsigned int RXCR1;
 volatile unsigned int RXCR2;
 volatile unsigned int RXBUF;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int IMCR;
 volatile unsigned int ICR;
} CSP_SIO_T, *CSP_SIO_PTR;



 typedef volatile struct
 {
    unsigned int CR;
    unsigned int TADDR;
    unsigned int SADDR;
    unsigned int ReservedD;
    unsigned int DATA_CMD;
    unsigned int SS_SCLH;
    unsigned int SS_SCLL;
    unsigned int FS_SCLH;
    unsigned int FS_SCLL;
    unsigned int ReservedA;
    unsigned int ReservedC;
    unsigned int RX_FLSEL;
    unsigned int TX_FLSEL;
    unsigned int RX_FL;
    unsigned int TX_FL;
    unsigned int ENABLE;
    unsigned int STATUS;
    unsigned int ReservedB;
    unsigned int SDA_TSETUP;
    unsigned int SDA_THOLD;
    unsigned int SPKLEN;

    unsigned int ReservedE;
 unsigned int MISR;
    unsigned int IMSCR;
    unsigned int RISR;
    unsigned int ICR;
    unsigned int ReservedF;
    unsigned int SCL_TOUT;
    unsigned int SDA_TOUT;
    unsigned int TX_ABRT;
    unsigned int GCALL;
    unsigned int NACK;
 } CSP_I2C_T, *CSP_I2C_PTR;



 typedef struct
 {
    volatile unsigned int CADATAH;
    volatile unsigned int CADATAL;
    volatile unsigned int CACON;
    volatile unsigned int INTMASK;
 } CSP_CA_T, *CSP_CA_PTR;



 typedef struct
 {
 volatile unsigned int CEDR;
 volatile unsigned int RSSR;
 volatile unsigned int PSCR;
 volatile unsigned int CR;
 volatile unsigned int SYNCR;
 volatile unsigned int GLDCR;
 volatile unsigned int GLDCFG;
 volatile unsigned int GLDCR2;
 volatile unsigned int Reserved0;
 volatile unsigned int PRDR;
 volatile unsigned int Reserved1;
 volatile unsigned int CMPA;
 volatile unsigned int CMPB;
 volatile unsigned int Reserved2;
 volatile unsigned int Reserved3;
 volatile unsigned int CMPLDR;
 volatile unsigned int CNT;
 volatile unsigned int AQLDR;
 volatile unsigned int AQCRA;
 volatile unsigned int AQCRB;
 volatile unsigned int Reserved4;
 volatile unsigned int Reserved5;
 volatile unsigned int Reserved6;
 volatile unsigned int AQOSF;
 volatile unsigned int AQCSF;
 volatile unsigned int Reserved7;
 volatile unsigned int Reserved8;
 volatile unsigned int Reserved9;
 volatile unsigned int Reserved10;
 volatile unsigned int Reserved11;
 volatile unsigned int Reserved12;
 volatile unsigned int Reserved13;
 volatile unsigned int Reserved14;
 volatile unsigned int Reserved15;
 volatile unsigned int Reserved16;
 volatile unsigned int Reserved17;
 volatile unsigned int Reserved18;
 volatile unsigned int Reserved19;
 volatile unsigned int Reserved20;
 volatile unsigned int Reserved21;
 volatile unsigned int Reserved22;
 volatile unsigned int Reserved23;
 volatile unsigned int Reserved24;
 volatile unsigned int Reserved25;
 volatile unsigned int Reserved26;
 volatile unsigned int Reserved27;
 volatile unsigned int TRGFTCR;
 volatile unsigned int TRGFTWR;
 volatile unsigned int EVTRG;
 volatile unsigned int EVPS;
 volatile unsigned int EVCNTINIT;
 volatile unsigned int EVSWF;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int IMCR;
 volatile unsigned int ICR;
 volatile unsigned int REGLINK;

 }CSP_GPT_T,*CSP_GPT_PTR;



 typedef struct
 {
   volatile unsigned int CEDR;
   volatile unsigned int RSSR;
   volatile unsigned int PSCR;
   volatile unsigned int CR;
   volatile unsigned int SYNCR;
   volatile unsigned int GLDCR;
   volatile unsigned int GLDCFG;
   volatile unsigned int GLDCR2;
   volatile unsigned int HRCFG;
   volatile unsigned int PRDR;
   volatile unsigned int PHSR;
   volatile unsigned int CMPA;
   volatile unsigned int CMPB;
   volatile unsigned int CMPC;
   volatile unsigned int CMPD;
   volatile unsigned int CMPLDR;
   volatile unsigned int CNT;
   volatile unsigned int AQLDR;
   volatile unsigned int AQCRA;
   volatile unsigned int AQCRB;
   volatile unsigned int AQCRC;
   volatile unsigned int AQCRD;
   volatile unsigned int AQTSCR;
   volatile unsigned int AQOSF;
   volatile unsigned int AQCSF;
   volatile unsigned int DBLDR;
   volatile unsigned int DBCR;
   volatile unsigned int DPSCR;
   volatile unsigned int DBDTR;
   volatile unsigned int DBDTF;
   volatile unsigned int CPCR;
   volatile unsigned int EMSRC;
   volatile unsigned int EMSRC2;
   volatile unsigned int EMPOL;
   volatile unsigned int EMECR;
   volatile unsigned int EMOSR;
   volatile unsigned int Reserved;
   volatile unsigned int EMSLSR;
   volatile unsigned int EMSLCLR;
   volatile unsigned int EMHLSR;
   volatile unsigned int EMHLCLR;
   volatile unsigned int EMFRCR;
   volatile unsigned int EMRISR;
   volatile unsigned int EMMISR;
   volatile unsigned int EMIMCR;
   volatile unsigned int EMICR;
   volatile unsigned int TRGFTCR;
   volatile unsigned int TRGFTWR;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVCNTINIT;
   volatile unsigned int EVSWF;
   volatile unsigned int RISR;
   volatile unsigned int MISR;
   volatile unsigned int IMCR;
   volatile unsigned int ICR;
   volatile unsigned int REGLINK;
   volatile unsigned int REGLINK2;
   volatile unsigned int REGPROT;
} CSP_EPT_T, *CSP_EPT_PTR;



 typedef volatile struct
 {
   volatile unsigned int CEDR;
   volatile unsigned int RSSR;
   volatile unsigned int PSCR;
   volatile unsigned int CR;
   volatile unsigned int SYNCR;
   volatile unsigned int PRDR;
   volatile unsigned int CMP;
   volatile unsigned int CNT;
   volatile unsigned int TRGFTCR;
   volatile unsigned int TRGFTWR;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVSWF;
   volatile unsigned int RISR;
   volatile unsigned int MISR;
   volatile unsigned int IMCR;
   volatile unsigned int ICR;
} CSP_LPT_T, *CSP_LPT_PTR;



 typedef struct
 {
   volatile unsigned int RSSR;
   volatile unsigned int CR;
   volatile unsigned int PSCR;
   volatile unsigned int PRDR;
   volatile unsigned int CMP;
   volatile unsigned int CNT;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVCNTINTI;
   volatile unsigned int EVSWF;
   volatile unsigned int RISR;
   volatile unsigned int IMCR;
   volatile unsigned int MISR;
   volatile unsigned int ICR;
} CSP_BT_T, *CSP_BT_PTR;



typedef struct
{
   volatile unsigned int IDR;
   volatile unsigned int CEDR;
   volatile unsigned int SRR;
   volatile unsigned int CR;
   volatile unsigned int SEED;
   volatile unsigned int DATAIN;
   volatile unsigned int DATAOUT;

} CSP_CRC_T, *CSP_CRC_PTR;



 typedef struct
 {
   volatile unsigned int TIMR;
   volatile unsigned int DATR;
   volatile unsigned int CR;
   volatile unsigned int CCR;
   volatile unsigned int ALRAR;
   volatile unsigned int ALRBR;
   volatile unsigned int SSR;
   volatile unsigned int CAL;
   volatile unsigned int RISR;
   volatile unsigned int IMCR;
   volatile unsigned int MISR;
   volatile unsigned int ICR;
   volatile unsigned int KEY;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVSWF;
} CSP_RTC_T, *CSP_RTC_PTR;




 typedef struct
 {
  volatile unsigned int CR;
  volatile unsigned int CFGR;
  volatile unsigned int RISR;
  volatile unsigned int MISR;
  volatile unsigned int IMCR;
  volatile unsigned int ICR;
 }CSP_WWDT_T,*CSP_WWDT_PTR;



 typedef struct
 {
  volatile S32_T DIVIDENT;
  volatile S32_T DIVISOR;
  volatile S32_T QUOTIENT;
  volatile S32_T REMAIN;
  volatile unsigned int CR;
 }CSP_HWD_T,*CSP_HWD_PTR;
# 691 "include/apt32f102.h"
extern CSP_CK801_T *CK801 ;

extern CSP_IFC_T *IFC ;
extern CSP_SYSCON_T *SYSCON ;
extern CSP_ETCB_T *ETCB ;

extern CSP_TKEY_T *TKEY ;
extern CSP_TKEYBUF_T *TKEYBUF ;
extern CSP_ADC12_T *ADC0 ;

extern CSP_GPIO_T *GPIOA0 ;
extern CSP_GPIO_T *GPIOB0 ;
extern CSP_IGRP_T *GPIOGRP ;

extern CSP_UART_T *UART0 ;
extern CSP_UART_T *UART1 ;
extern CSP_UART_T *UART2 ;
extern CSP_SSP_T *SPI0 ;
extern CSP_SIO_T *SIO0 ;
extern CSP_I2C_T *I2C0 ;
extern CSP_CA_T *CA0 ;

extern CSP_GPT_T *GPT0 ;

extern CSP_EPT_T *EPT0 ;

extern CSP_LPT_T *LPT ;
extern CSP_HWD_T *HWD ;
extern CSP_WWDT_T *WWDT ;
extern CSP_BT_T *BT0 ;
extern CSP_BT_T *BT1 ;

extern CSP_CRC_T *CRC ;
extern CSP_RTC_T *RTC ;


void MisalignedHandler(void) __attribute__((isr));
void IllegalInstrHandler(void) __attribute__((isr));
void AccessErrHandler(void) __attribute__((isr));
void BreakPointHandler(void) __attribute__((isr));
void UnrecExecpHandler(void) __attribute__((isr));
void Trap0Handler(void) __attribute__((isr));
void Trap1Handler(void) __attribute__((isr));
void Trap2Handler(void) __attribute__((isr));
void Trap3Handler(void) __attribute__((isr));
void PendTrapHandler(void) __attribute__((isr));

void CORETHandler(void) __attribute__((isr));
void SYSCONIntHandler(void) __attribute__((isr));
void IFCIntHandler(void) __attribute__((isr));
void ADCIntHandler(void) __attribute__((isr));
void EPT0IntHandler(void) __attribute__((isr));
void WWDTHandler(void) __attribute__((isr));
void EXI0IntHandler(void) __attribute__((isr));
void EXI1IntHandler(void) __attribute__((isr));
void EXI2to3IntHandler(void) __attribute__((isr));
void EXI4to9IntHandler(void) __attribute__((isr));
void EXI10to15IntHandler(void) __attribute__((isr));
void UART0IntHandler(void) __attribute__((isr));
void UART1IntHandler(void) __attribute__((isr));
void UART2IntHandler(void) __attribute__((isr));
void I2CIntHandler(void) __attribute__((isr));
void GPT0IntHandler(void) __attribute__((isr));
void LEDIntHandler(void) __attribute__((isr));
void TKEYIntHandler(void) __attribute__((isr));
void SPI0IntHandler(void) __attribute__((isr));
void SIO0IntHandler(void) __attribute__((isr));
void CNTAIntHandler(void) __attribute__((isr));
void RTCIntHandler(void) __attribute__((isr));
void LPTIntHandler(void) __attribute__((isr));
void BT0IntHandler(void) __attribute__((isr));
void BT1IntHandler(void) __attribute__((isr));

extern int __divsi3 (int a, int b);
extern unsigned int __udivsi3 (unsigned int a, unsigned int b);
extern int __modsi3 (int a, int b);
extern unsigned int __umodsi3 (unsigned int a, unsigned int b);
extern void delay_nms(unsigned int t);
extern void delay_nus(unsigned int t);
# 25 "include/apt32f102_i2c.h" 2
# 169 "include/apt32f102_i2c.h"
typedef enum
{
    I2C_SDA_PA00= 0,
 I2C_SDA_PA03 = 1,
 I2C_SDA_PA07= 2,
    I2C_SDA_PA013= 3,
    I2C_SDA_PA014 = 4,
}I2C_SDA_TypeDef;




typedef enum
{
    I2C_SCL_PB00 = 0,
 I2C_SCL_PB02 = 1,
    I2C_SCL_PA01 = 2,
    I2C_SCL_PA04 = 3,
 I2C_SCL_PA06 = 4,
 I2C_SCL_PA015 = 5,
}I2C_SCL_TypeDef;




typedef enum
{
 STANDARD_MODE = (0x01ul << 1),
    FAST_MODE=(0x02ul << 1),
}I2C_SPEEDMODE_TypeDef;




typedef enum
{
 I2C_SLAVE_7BIT= (0x00ul << 3),
    I2C_SLAVE_10BIT=(0x01ul << 3),
}I2C_SLAVEBITS_TypeDef;




typedef enum
{
 I2C_MASTRER_7BIT= (0x00ul << 4),
    I2C_MASTRER_10BIT=(0x01ul << 4),
}I2C_MASTRERBITS_TypeDef;




extern void I2C_Master_CONFIG(I2C_SDA_TypeDef I2C_SDA_IO,I2C_SCL_TypeDef I2C_SCL_IO,I2C_SPEEDMODE_TypeDef SPEEDMODE,
        I2C_MASTRERBITS_TypeDef MASTERBITS,U16_T I2C_MASTER_ADD,U16_T SS_SCLH,U16_T SS_SCLL);
extern void I2C_Slave_CONFIG(I2C_SDA_TypeDef I2C_SDA_IO,I2C_SCL_TypeDef I2C_SCL_IO,I2C_SPEEDMODE_TypeDef SPEEDMODE,
      I2C_SLAVEBITS_TypeDef SLAVEBITS,U16_T I2C_SALVE_ADDS,U16_T SS_SCLHX,U16_T SS_SCLLX);
extern void I2C_SDA_TSETUP_THOLD_CONFIG(U8_T SDA_TSETUP , U8_T SDA_RX_THOLD , U16_T SDA_TX_THOLD);
extern void I2C_ConfigInterrupt_CMD(FunctionalStatus NewState,U32_T INT_TYPE);
extern void I2C_FIFO_TriggerData(U16_T RX_FLSEL,U16_T TX_FLSEL);
extern void I2C_Stop(void);
extern void I2C_Enable(void);
extern void I2C_Disable(void);
extern void I2C_Abort_EN(void);
extern U8_T I2C_Abort_Status(void);
extern void I2C_SDA_Recover_EN(void);
extern void I2C_SDA_Recover_DIS(void);
extern void I2C_Int_Enable(void);
extern void I2C_Int_Disable(void);
extern void I2C_WRITE_Byte(U8_T write_adds,U8_T i2c_data);
extern void I2C_WRITE_nByte(U8_T write_adds,volatile U8_T *i2c_data,U8_T NumByteToWrite);
extern U8_T I2C_READ_Byte(U8_T read_adds);
extern void I2C_READ_nByte(U8_T read_adds,volatile U8_T *i2c_data,U8_T NumByteToWrite);
extern void I2C_Slave_Receive(void);
extern void I2C_DeInit(void);

extern volatile unsigned char I2CWrBuffer[32];
extern volatile unsigned char I2CRdBuffer[32];
extern volatile U8_T f_ERROR;
extern void I2C_SLAVE_CONFIG(void);
# 18 "FWlib/apt32f102_i2c.c" 2
volatile unsigned char I2CWrBuffer[32];
volatile unsigned char I2CRdBuffer[32];
volatile unsigned char RdIndex = 0;
volatile unsigned char WrIndex = 0;
volatile unsigned char I2C_Data_Adress;
volatile unsigned char I2C_St_Adress;
volatile U8_T f_ERROR=0;
volatile U32_T R_IIC_ERROR_CONT;
extern void delay_nms(unsigned int t);





void I2C_DeInit(void)
{
    I2C0->ENABLE = 0;
    I2C0->IMSCR = 0;
    I2C0->ICR = 0X7FFF;
}







void I2C_Master_CONFIG(I2C_SDA_TypeDef I2C_SDA_IO,I2C_SCL_TypeDef I2C_SCL_IO,I2C_SPEEDMODE_TypeDef SPEEDMODE,
      I2C_MASTRERBITS_TypeDef MASTERBITS,U16_T I2C_MASTER_ADDS,U16_T SS_SCLHX,U16_T SS_SCLLX)
{

    if(I2C_SDA_IO==I2C_SDA_PA00)
    {
    GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFF0) | 0x00000005;
    }
    else if(I2C_SDA_IO==I2C_SDA_PA03)
    {
    GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x00006000;
    }
 else if (I2C_SDA_IO==I2C_SDA_PA07)
    {
    GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF) | 0x40000000;
    }
 else if(I2C_SDA_IO==I2C_SDA_PA013)
    {
    GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF) | 0x00600000;
    }
 else if(I2C_SDA_IO==I2C_SDA_PA014)
    {
    GPIOA0->CONHR = (GPIOA0->CONHR&0XF0FFFFFF) | 0x06000000;
    }

 if (I2C_SCL_IO==I2C_SCL_PB00)
    {
    GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0) | 0x00000006;
    }
 else if (I2C_SCL_IO==I2C_SCL_PB02)
    {
    GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF) | 0x00000400;
    }
    else if(I2C_SCL_IO==I2C_SCL_PA01)
    {
    GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF0F) | 0x00000050;
    }
    else if(I2C_SCL_IO==I2C_SCL_PA04)
    {
     GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF0FFFF) | 0x00060000;
    }
 else if(I2C_SCL_IO==I2C_SCL_PA06)
    {
    GPIOA0->CONLR = (GPIOA0->CONLR&0XF0FFFFFF) | 0x06000000;
    }
 else if(I2C_SCL_IO==I2C_SCL_PA015)
    {
    GPIOA0->CONHR = (GPIOA0->CONHR&0X0FFFFFFF) | 0x60000000;
    }
 I2C0->ENABLE = (I2C0->ENABLE&0XFFFFFFFE)|(0x00ul << 0);
 I2C0->CR =(I2C0->CR&0XFFFFF000)|(0x01ul << 0) |(0x01ul << 6)| SPEEDMODE | MASTERBITS | (0x01ul << 5);
 I2C0->TADDR =I2C_MASTER_ADDS;
 if(SPEEDMODE==FAST_MODE)
 {
  I2C0->FS_SCLH = SS_SCLHX;
  I2C0->FS_SCLL = SS_SCLLX;
 }
 else if(SPEEDMODE==STANDARD_MODE)
 {
  I2C0->SS_SCLH = SS_SCLHX;
  I2C0->SS_SCLL = SS_SCLLX;
 }

}
# 117 "FWlib/apt32f102_i2c.c"
void I2C_Slave_CONFIG(I2C_SDA_TypeDef I2C_SDA_IO,I2C_SCL_TypeDef I2C_SCL_IO,I2C_SPEEDMODE_TypeDef SPEEDMODE,
      I2C_SLAVEBITS_TypeDef SLAVEBITS,U16_T I2C_SALVE_ADDS,U16_T SS_SCLHX,U16_T SS_SCLLX)
{

    if(I2C_SDA_IO==I2C_SDA_PA00)
    {
    GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFF0) | 0x00000005;
    }
    else if(I2C_SDA_IO==I2C_SDA_PA03)
    {
    GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x00006000;
    }
 else if (I2C_SDA_IO==I2C_SDA_PA07)
    {
    GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF) | 0x40000000;
    }
 else if(I2C_SDA_IO==I2C_SDA_PA013)
    {
    GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF) | 0x00600000;
    }
 else if(I2C_SDA_IO==I2C_SDA_PA014)
    {
    GPIOA0->CONHR = (GPIOA0->CONHR&0XF0FFFFFF) | 0x06000000;
    }

 if (I2C_SCL_IO==I2C_SCL_PB00)
    {
    GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0) | 0x00000006;
    }
 else if (I2C_SCL_IO==I2C_SCL_PB02)
    {
    GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF) | 0x00000400;
    }
    else if(I2C_SCL_IO==I2C_SCL_PA01)
    {
    GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF0F) | 0x00000050;
    }
    else if(I2C_SCL_IO==I2C_SCL_PA04)
    {
     GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF0FFFF) | 0x00060000;
    }
 else if(I2C_SCL_IO==I2C_SCL_PA06)
    {
    GPIOA0->CONLR = (GPIOA0->CONLR&0XF0FFFFFF) | 0x06000000;
    }
 else if(I2C_SCL_IO==I2C_SCL_PA015)
    {
    GPIOA0->CONHR = (GPIOA0->CONHR&0X0FFFFFFF) | 0x60000000;
    }
 I2C0->ENABLE = (I2C0->ENABLE&0XFFFFFFFE)|(0x00ul << 0);
 I2C0->CR =(I2C0->CR&0XFFFFF000)| (0x00ul << 0) |(0x00ul << 6) | SPEEDMODE | SLAVEBITS;
 I2C0->SADDR = I2C_SALVE_ADDS;
 if(SPEEDMODE==FAST_MODE)
 {
  I2C0->FS_SCLH = SS_SCLHX;
  I2C0->FS_SCLL = SS_SCLLX;
 }
 else if(SPEEDMODE==STANDARD_MODE)
 {
  I2C0->SS_SCLH = SS_SCLHX;
  I2C0->SS_SCLL = SS_SCLLX;
 }
}





void I2C_SDA_TSETUP_THOLD_CONFIG(U8_T SDA_TSETUP , U8_T SDA_RX_THOLD , U16_T SDA_TX_THOLD)
{
 I2C0->SDA_TSETUP=SDA_TSETUP;
 I2C0->SDA_THOLD=(SDA_RX_THOLD<<16)|SDA_TX_THOLD;
}
# 199 "FWlib/apt32f102_i2c.c"
void I2C_ConfigInterrupt_CMD(FunctionalStatus NewState,U32_T INT_TYPE)
{
 if(NewState != DISABLE)
 {
  I2C0->IMSCR |= INT_TYPE;
 }
 else
 {
  I2C0->IMSCR &= (~INT_TYPE);
 }
}





void I2C_FIFO_TriggerData(U16_T RX_FLSEL,U16_T TX_FLSEL)
{
 I2C0->RX_FLSEL = RX_FLSEL;
 I2C0->TX_FLSEL = TX_FLSEL;
}





void I2C_Stop(void)
{
 I2C0->DATA_CMD = (I2C0->DATA_CMD&0XFFFFFDFF)|(0x01ul << 9);
}





void I2C_Enable(void)
{
 I2C0->ENABLE = (I2C0->ENABLE&0XFFFFFFFE)|(0x01ul << 0);
 while((I2C0->STATUS&0x1000)!=0x1000);
}





void I2C_Disable(void)
{
 I2C0->ENABLE =(I2C0->ENABLE&0XFFFFFFFE)|(0x00ul << 0);
 while((I2C0->STATUS&0x1000)==0x1000);
}





void I2C_Abort_EN(void)
{
 I2C0->ENABLE = (I2C0->ENABLE&0XFFFFFFFD)|(0x01ul << 1);
}





U8_T I2C_Abort_Status(void)
{
 unsigned char value = 0;
    unsigned int dat = 0;
 dat=(I2C0->ENABLE)&0x02;
    if (dat == 0x02)
 {
     value = 1;
 }
    return value;
}





void I2C_SDA_Recover_EN(void)
{
 I2C0->ENABLE = (I2C0->ENABLE&0XFFFFFFF7)|(0x01ul << 3);
}





void I2C_SDA_Recover_DIS(void)
{
 I2C0->ENABLE = (I2C0->ENABLE&0XFFFFFFF7)|(0x00ul << 3);
}





void I2C_Int_Enable(void)
{
 *(volatile UINT32 *) (0xE000E000 +0x100 ) = (0x01ul<<17);
}





void I2C_Int_Disable(void)
{
    *(volatile UINT32 *) (0xE000E000 +0x180 ) = (0x01ul<<17);
}





void I2C_WRITE_Byte(U8_T write_adds,U8_T i2c_data)
{
 U16_T R_EEROR_CONT=0;

 I2C0->DATA_CMD = (0x00ul << 8)|write_adds ;
 I2C0->DATA_CMD = i2c_data |(0x01ul << 9);
 do
 {
  if(R_EEROR_CONT++>=10000)
  {
   R_EEROR_CONT=0;
   f_ERROR=1;
   I2C_Disable();
   I2C_Enable();
   break;
  }
 }
 while( (I2C0->STATUS & (0x01ul << 0)) != (0x01ul << 0) );
 do
 {
  if(R_EEROR_CONT++>=10000)
  {
   R_EEROR_CONT=0;
   f_ERROR=1;
   I2C_Disable();
   I2C_Enable();
   break;
  }
 }
 while(((I2C0->STATUS) & (0x01ul << 2)) != (0x01ul << 2));
}





void I2C_WRITE_nByte(U8_T write_adds,volatile U8_T *i2c_data,U8_T NumByteToWrite)
{
 U16_T R_EEROR_CONT=0;
 U8_T i;
 I2C0->DATA_CMD = (0x00ul << 8)|write_adds ;
 for(i=0;i<NumByteToWrite;i++)
 {
  if(i>=NumByteToWrite-1)
  {
   I2C0->DATA_CMD = *(i2c_data+i) |(0x01ul << 9);
  }
  else
  {
   I2C0->DATA_CMD = *(i2c_data+i);
  }
  do
  {
   if(R_EEROR_CONT++>=10000)
   {
    R_EEROR_CONT=0;
    f_ERROR=1;
    I2C_Disable();
    I2C_Enable();
    break;
   }
  }
  while( (I2C0->STATUS & (0x01ul << 0)) != (0x01ul << 0) );
  do
  {
   if(R_EEROR_CONT++>=10000)
   {
    R_EEROR_CONT=0;
    f_ERROR=1;
    I2C_Disable();
    I2C_Enable();
    break;
   }
  }
  while(((I2C0->STATUS) & (0x01ul << 1)) != (0x01ul << 1));
 }
}





U8_T I2C_READ_Byte(U8_T read_adds)
{
 U8_T value;
 U16_T R_EEROR_CONT=0;
 I2C0->DATA_CMD = (0x00ul << 8)|read_adds|(0x01ul <<10);
 I2C0->DATA_CMD = (0x01ul << 8) |(0x01ul << 9);
 do
 {
  if(R_EEROR_CONT++>=10000)
  {
   R_EEROR_CONT=0;
   f_ERROR=1;
   break;
  }
 }
 while( (I2C0->STATUS & (0x01ul << 0)) != (0x01ul << 0) );
 do
 {
  if(R_EEROR_CONT++>=10000)
  {
   R_EEROR_CONT=0;
   f_ERROR=1;
   break;
  }
 }
 while( (I2C0->STATUS & (0x01ul << 3)) != (0x01ul << 3) );
 value=I2C0->DATA_CMD &0XFF;
 return value;
}





void I2C_READ_nByte(U8_T read_adds,volatile U8_T *i2c_data,U8_T NumByteToWrite)
{
 U16_T R_EEROR_CONT=0;
 U8_T i;
 I2C0->DATA_CMD = (0x00ul << 8)|read_adds|(0x01ul <<10);
 for(i=0;i<NumByteToWrite;i++)
 {
  if(i>=NumByteToWrite-1)
  {
   I2C0->DATA_CMD = (0x01ul << 8) |(0x01ul << 9);
  }
  else
  {
   I2C0->DATA_CMD = (0x01ul << 8);
  }
  do
  {
   if(R_EEROR_CONT++>=10000)
   {
    R_EEROR_CONT=0;
    f_ERROR=1;
    break;
   }
  }
  while( (I2C0->STATUS & (0x01ul << 0)) != (0x01ul << 0) );
  do
  {
   if(R_EEROR_CONT++>=10000)
   {
    R_EEROR_CONT=0;
    f_ERROR=1;
    break;
   }
  }
  while( (I2C0->STATUS & (0x01ul << 3)) != (0x01ul << 3) );
  *(i2c_data+i)=I2C0->DATA_CMD &0XFF;
 }
}
U16_T R_READ_BUF=0;





void I2C_Slave_Receive(void)
{

 if(!(((I2C0->MISR&(0x01ul <<14))==(0x01ul <<14))
   ||((I2C0->MISR&(0x01ul << 6))==(0x01ul << 6))))
 {
 if((I2C0->MISR&(0x01ul << 2))==(0x01ul << 2))
 {
  if(RdIndex==0)
  {
   RdIndex=1;
   I2C_Data_Adress=I2C0->DATA_CMD&0XFF;
   I2C_St_Adress=I2C_Data_Adress;
  }
  else
  {
   if(I2C_Data_Adress<32)
   {
    I2CRdBuffer[I2C_Data_Adress]= I2C0->DATA_CMD&0XFF;
   }
   I2C_Data_Adress++;
  }
  I2C0->ICR = (0x01ul << 2);
  R_IIC_ERROR_CONT=0;
 }

 if((I2C0->MISR&(0x01ul << 5))==(0x01ul << 5))
 {
  if(RdIndex==1)
  {
   RdIndex=2;
   WrIndex = I2C_St_Adress;

   if(WrIndex<32)
   {
    I2C0->DATA_CMD= (I2C0->DATA_CMD&0XFFFFFF00) |I2CWrBuffer[WrIndex];
   }
  }
  I2C0->ICR = (0x01ul << 5);
  R_IIC_ERROR_CONT=0;
 }

 if((I2C0->MISR&(0x01ul << 4))==(0x01ul << 4))
 {
  if(RdIndex==2)
  {
   if(WrIndex+1<32)
   {
    I2C0->DATA_CMD= (I2C0->DATA_CMD&0XFFFFFF00) |I2CWrBuffer[WrIndex+1];
   }
   WrIndex++;
  }
  else
  {
   if(R_IIC_ERROR_CONT>10000)
   {
    I2C_Disable();
    I2C0->DATA_CMD= (I2C0->DATA_CMD&0XFFFFFF00);
    I2C_SLAVE_CONFIG();
    R_IIC_ERROR_CONT=0;
   }
   else
   {
    R_IIC_ERROR_CONT++;
   }
  }
  I2C0->CR = (0x01ul << 4);
 }

 else if((I2C0->MISR&(0x01ul << 9))==(0x01ul << 9))
 {
  I2C0->ICR =(0x01ul << 9);
  if(RdIndex!=0)
  {
   RdIndex=0;

  }
  R_READ_BUF=I2C0->DATA_CMD&0XFF;
  R_IIC_ERROR_CONT=0;
 }
}
else
{
  I2C_Disable();
  I2C0->DATA_CMD= (I2C0->DATA_CMD&0XFFFFFF00);
  I2C_SLAVE_CONFIG();
  RdIndex=0;

  I2C0->ICR = (0x01ul <<14)|(0x01ul << 6);
  R_IIC_ERROR_CONT=0;

}
}
